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BCM2835 ARM Peripherals

© 2012 Broadcom Corporation. All rights reserved
Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW

Table of Contents
1 Introduction 1.1 Overview 1.2 Address map 1.2.1 Diagrammatic overview ARM virtual addresses (standard Linux kernel only) 1.2.2 1.2.3 ARM physical addresses 1.2.4 Bus addresses 1.3 Peripheral access precautions for correct memoryordering 2 Auxiliaries: UART1 & SPI1, SPI2 2.1 Overview 2.1.1 AUX registers 2.2 Mini UART 2.2.1 Mini UART implementation details. 2.2.2 Mini UART register details. 2.3 Universal SPI Master (2x) 2.3.1 SPI implementation details 2.3.2 Interrupts 2.3.3 Long bit streams 2.3.4 SPI register details. 3 BSC 3.1 Introduction 3.2 Register View 3.3 10 Bit Addressing 4 DMA Controller 4.1 Overview 4.2 DMAController Registers 4.2.1 DMA Channel Register Address Map 4.3 AXI Bursts 4.4 Error Handling 4.5 DMA LITE Engines 5 o o External Mass Media Controller Introduction Registers 4 4 4 4 6 6 6 7 8 8 9 10 11 11 20 20 21 21 22 28 28 28 36 38 38 39 40 63 63 63 65 65 66 89 90 102 105 109 109 110 110 110 112 119 120 120 121 122 122 123 Page ii

6 General Purpose I/O (GPIO) 6.1 Register View 6.2 AlternativeFunction Assignments 6.3 General Purpose GPIO Clocks 7 Interrupts 7.1 Introduction 7.2 Interrupt pending. 7.3 Fast Interrupt (FIQ). 7.4 Interrupt priority. Registers 7.5 8 PCM / I2S Audio 8.1 Block Diagram Typical Timing 8.2 8.3 Operation 8.4 Software Operation 8.4.1 Operating in Polled mode 8.4.2 Operating in Interrupt mode 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton RoadCambridge CB4 0WW © 2012 Broadcom Corporation. All rights reserved

8.4.3 8.5 8.6 8.7 8.8

DMA Error Handling. PDM Input Mode Operation GRAY Code Input Mode Operation PCM Register Map

123 123 124 124 125 138 138 138 139 139 140 141 148 148 148 148 149 150 150 150 151 151 151 152 152 158 158 158 158 159 160 160 160 172 172 175 175 176 176 177 196 196 196 200 200 202

9 Pulse Width Modulator 9.1Overview 9.2 Block Diagram 9.3 PWM Implementation 9.4 Modes of Operation 9.5 Quick Reference 9.6 Control and Status Registers 10 SPI 10.1 10.2 10.2.1 10.2.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.4 10.5 10.6 10.6.1 10.6.2 10.6.3 10.6.4

Introduction SPI Master Mode Standard mode Bidirectional mode LoSSI mode Command write Parameter write Byte read commands 24bit read command 32bit readcommand Block Diagram SPI Register Map Software Operation Polled Interrupt DMA Notes

11 SPI/BSC SLAVE 11.1 Introduction 11.2 Registers 12 System Timer 12.1 System Timer Registers 13 UART 13.1 Variations from the 16C650 UART 13.2 Primary UART Inputs and Outputs 13.3 UART Interrupts 13.4 Register View 14 Timer (ARM side) 14.1 Introduction 14.2 Timer Registers: 15 USB 15.1 Configuration 15.2 Extra /Adapted registers.

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW © 2012 Broadcom Corporation. All rights reserved

Page iii

1 Introduction
1.1 Overview

BCM2835 contains the following peripherals which may safely be accessed by the ARM: • • • • • • • • • • • Timers Interrupt controller GPIO USB PCM / I2S DMA controller I2C master I2C / SPI slaveSPI0, SPI1, SPI2 PWM UART0, UART1

The purpose of this datasheet is to provide documentation for these peripherals in sufficient detail to allow a developer to port an operating system to BCM2835. There are a number of peripherals which are intended to be controlled by the GPU. These are omitted from this datasheet. Accessing these peripherals from the ARM is not recommended. 1.2 Address map1.2.1 Diagrammatic overview In addition to the ARM’s MMU, BCM2835 includes a second coarse-grained MMU for mapping ARM physical addresses onto system bus addresses. This diagram shows the main address spaces of interest:

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW © 2012 Broadcom Corporation. All rights reserved

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06 February 2012 Broadcom...
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