IR2112(S) & (PbF)
HIGH AND LOW SIDE DRIVER
• Floating channel designed for bootstrap operation • Fully operational to +600V • Tolerant to negative transient voltage • Gate drive supply range from 10 to 20V • Undervoltage lockout for both channels • 3.3V logic compatible • • • • •
Separate logic supply range from 3.3V to 20V Logic and power ground ±5Voffset CMOS Schmitt-triggered inputs with pull-down Cycle by cycle edge-triggered shutdown logic Matched propagation delay for both channels Outputs in phase with inputs Also available LEAD-FREE dV/dt immune
VOFFSET IO+/VOUT ton/off (typ.) Delay Matching 600V max. 200 mA / 420 mA 10 - 20V 125 & 105 ns 30 ns
The IR2112(S) is a high voltage, high speedpower MOSFET and IGBT driver with independent high and 16-Lead SOIC low side referenced output channels. Proprietary HVIC (wide body) 14-Lead PDIP and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum drivercrossconduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts.
HO VDD HIN SD LIN VSS VCC VDD HIN SD LIN VSS VCC COM LO VB VS
up to 600V
(Refer to Lead Assignments for correct pinconfiguration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
IR2112(S) & (PbF)
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Thermal Resistanceand Power Dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.
VB VS VHO VCC VLO VDD VSS VIN dVs/dt PD RTHJA TJ TS TL
High Side Floating Supply Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Fixed Supply Voltage Low Side Output Voltage LogicSupply Voltage Logic Supply Offset Voltage Logic Input Voltage (HIN, LIN & SD) Allowable Offset Supply Voltage Transient (Figure 2) Package Power Dissipation @ TA ≤ +25° C Thermal Resistance, Junction to Ambient Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) (14 Lead DIP) (16 Lead SOIC) (14 Lead DIP) (16 Lead SOIC)
-0.3 VB - 25 VS - 0.3 -0.3 -0.3 -0.3 VCC -25 VSS - 0.3 — — — — — — -55 —
625 VB + 0.3 VB + 0.3 25 VCC + 0.3 VSS + 25 VCC + 0.3 VDD + 0.3 50 1.6 1.25 75 100 150 150 300
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS and V SS offset ratings are tested withall supplies biased at 15V differential. Typical ratings at other bias conditions are shown in Figures 36 and 37.
VB VS VHO VCC VLO VDD VSS VIN TA
High Side Floating Supply Absolute Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Fixed Supply Voltage Low Side Output Voltage Logic Supply Voltage Logic Supply Offset Voltage LogicInput Voltage (HIN, LIN & SD) Ambient Temperature
VS + 10 Note 1 VS 10 0 VSS + 3 -5 (Note 2) VSS -40
VS + 20 600 VB 20 VCC VSS + 20 5 VDD 125
Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip DT97-3 for more details). Note 2: When VDD < 5V, the minimum VSS offset is limited to -VDD.