Artigo 1

FUNCTIONAL VERIFICATION OF VERILOG DESIGN USING A VERISC METHODOLOGY TESTBENCH APPROACH
Adriana Ferreira de Brito, Raphael de Souza Neves, Karina Rocha Gomes da Silva Escola de Engenharia Elétrica, Mecânica e de Computação Universidade Federal de Goiás (UFG)
ABSTRACT Functional verification is a very difficult part of the entire chip design. It spends almost 70% of the resources. The focus of this work is to propose a functional verification methodology for Verilog designs, using the VeriSC methodology [1] as a basis, and using the Verilog language to implement the testbench. With this methodology will be possible to design a testbench that can identify functional errors as soon as possible in the Design Under Verification (DUV). 1. INTRODUCTION Verification aims to ensure that the results of a design is consistent with the expected. One way to make a verification process more efficient would be automating it, making the process faster and more predictable [2]. The testbench is an option to conduct the verification in order to focus on identify the errors as soon as possible, because if the errors propagate to the other phases from the design, it became more difficult to catch them. The testbench is an environment in which the device to be verified (Design Under Verification – DUV) receive the specified stimuli and it results can be compared with the ideal results, coming from the reference model. With VeriSC methodology the implementation of the testbench is performed before to start the development of the DUV, together with the development of the reference model [1]. There are three types of verification: static, dynamic and hybrid, the dynamic verification is known as functional verification “it is the default strategy of the CIs industry” [3]. Functional Verification has a testbench, that is an environment composed of reference model (ideal model), implementing all specified features of device [1] and the design Under verification (DUV). The testbench is