Flash specs

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Open NAND Flash Interface Specification

Revision 1.0 28-December-2006

Hynix Semiconductor Intel Corporation Micron Technology, Inc. Phison Electronics Corp. Sony Corporation STMicroelectronics

This 1.0 revision of the Open NAND Flash Interface specification ("Final Specification") is available for download at www.onfi.org. SPECIFICATION DISCLAIMER THIS SPECIFICATION IS PROVIDED TOYOU “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE. THE AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO USE OR IMPLEMNETATION OF INFORMATION IN THIS SPECIFICATION. THE AUTHORS DO NOT WARRANT OR REPRESENT THAT SUCH USE WILL NOTINFRINGE SUCH RIGHTS. THE PROVISION OF THIS SPECIFICATION TO YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS. Copyright 2005-2006, Hynix Semiconductor, Intel Corporation, Micron Technology, Inc., Phison Electronics Corp., Sony Corporation, STMicroelectronics. All rights reserved. For more information about ONFI, referto the ONFI Workgroup website at www.onfi.org. All product names are trademarks, registered trademarks, or servicemarks of their respective owners. ONFI Workgroup Technical Editor: Amber Huffman Intel Corporation 2111 NE 25th Ave M/S JF2-53 Hillsboro, OR 97124 USA Tel: (503) 264-7929 Email: amber.huffman@intel.com

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Table of Contents
Introduction........................................................................................................................... 1 1.1. Goals and Objectives ........................................................................................................ 1 1.2. References ........................................................................................................................ 1 1.3. Definitions, abbreviations, andconventions...................................................................... 1 1.3.1. Definitions and Abbreviations .................................................................................... 1 1.3.2. Conventions ............................................................................................................... 3 2. Physical Interface................................................................................................................. 6 2.1. TSOP-48 and WSOP-48 Pin Assignments ....................................................................... 6 2.2. LGA-52 Pad Assignments................................................................................................. 7 2.3. BGA-63 BallAssignments................................................................................................. 8 2.4. Signal Descriptions ......................................................................................................... 11 2.5. CE# Signal Requirements............................................................................................... 14 2.6. Absolute Maximum Ratings............................................................................................ 14 2.7. Recommended Operating Conditions ............................................................................. 15 2.7.1. Provisions for I/O power (Vccq) and I/O ground (Vssq) .......................................... 15 2.8. DC and Operating Characteristics .................................................................................. 152.9. Calculating Pin Capacitance ........................................................................................... 17 2.10. Staggered Power-up.................................................................................................... 17 2.11. Independent Data Buses ............................................................................................. 18 2.12. Bus Width...
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