Projeto fpga

franz_vitor.vhd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 library ieee; use ieee.std_logic_1164.all; entity VERIFICA_SENHA is port(clk50: in std_logic; botao0,botao1,botao2,botao3: in std_logic; a: in std_logic; l: out std_logic; s: out std_logic; an: out std_logic_vector(3 downto 0); disp: out std_logic_vector(6 downto 0)); end verifica_senha;

Mon Dec 13 09:40:16 2010

architecture a of VERIFICA_SENHA is signal clk10: std_logic; signal clk500: std_logic; signal d: std_logic:='0'; signal t: std_logic; signal i: std_logic; signal c: std_logic; signal valor: integer range 0 to 3; signal m: std_logic_vector(1 downto 0); signal b0: std_logic:='0'; signal b1: std_logic:='0' ; signal b2: std_logic:='0' ; signal b3: std_logic:='0' ; signal b0aux: std_logic:='0'; signal b1aux: std_logic:='0' ; signal b2aux: std_logic:='0' ; signal b3aux: std_logic:='0' ; signal cont10khz: integer range 0 to 4999; signal cont500hz: integer range 0 to 19; signal senha: integer range 0 to 3; signal contador: integer range 0 to 50000; signal tempo: integer range 0 to 40000; signal e: std_logic; type statet is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18, s19,s20,s21,s22,s23); signal estado: statet:=s0; signal selecao: integer range 0 to 3; signal debounce0: integer range 0 to 9999; signal debounce1: integer range 0 to 9999; signal debounce2: integer range 0 to 9999; signal debounce3: integer range 0 to 9999;

begin --cria um clk de 10khz process(clk50) begin if rising_edge(clk50) then