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Advanced Programmable Interrupt Controller

Advanced Programmable Interrupt Controller
by Mike Rieker
Though I had originally wrote my APIC code over a year ago, I've been playing with it recently, so I thought I'd write about it. This is not a complete treatment, but it contains stuff that the docs for the chips don't seem to tell. There are basically two things here to consider. 1. Builtinto all recent x86 CPU chips (Pent Pro and up) is a thing called a Local APIC. It is addressed at physical addresses FEE00xxx. Actually, that is the default, it can be moved by programming the MSR that holds it base address. It has many fun things in it. The big thing is that you can interrupt other CPU's in a multiprocessor system. But if you just have a uniprocessor, there are useful things forit, too. The Local APIC is described in Chapter 7 of Volume 3 of the Intel processor books. 2. Some motherboards have an IO APIC on them. This is usually only found on multiprocessor boards. Functionally, it replaces the 8259's. You must essentially shut off the 8259's and turn on the IO APIC to use it. The IO APIC is typically located at physical address FEC00000, but may be moved by programmingthe north/southbridge chipset. The Intel chip number is 82093 and you can get the doc for it off of the Intel website.

What the Local APIC Is
As stated above, the Local APIC (LAPIC) is a circuit that is part of the CPU chip. It contains these basic elements: 1. A mechanism for generating interrupts 2. A mechanism for accepting interrupts 3. A timer If you have a multiprocessor system, theAPIC's are wired together so they can communicate. So the LAPIC on CPU 0 can communicate with the LAPIC on CPU 1, etc.

What the IO APIC Is
This is a separate chip that is wired to the Local APIC's so it can forward interrupts on to the CPU chips. It is programmed similar to the 8259's but has more flexibility. It is wired to the same bus as the Local APIC's so it can communicate with them.

Funthings to do with a Local APIC in a Uniprocessor

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Advanced Programmable Interrupt Controller

(this stuff also applies to multiprocessors, too)
One thing the LAPIC can help with is the following problem: An IRQ-type interrupt routine wishes to wake a sleeping thread, but this IRQ interrupt may be nested several levels inside other IRQ interrupts, so it cannot simply switch stacks asthose outer interrupt routines would not complete until the old thread is re-woken. So we have to somehow switch out of the current thread and switch into the thread to be woken. A way the LAPIC can help us is to tell it to interrupt this same CPU, but only when there are no IRQ-type interrupt handlers active. I call this a 'software' interrupt because the operating system software initiated theinterrupt. It is programmed into the LAPIC to be at a priority lower than any IRQ-type interrupt. So now if some IRQ-type routine wants to wake a thread, it makes the necessary changes to the datastructures, then triggers a software interrupt to itself. Then, when all IRQ-type interrupt handlers have returned out, the LAPIC is now able to interrupt.It interrupts out of the currently executingthread and switches to the thread that was just woken. Very neat. Without the LAPIC, your interrupt routine has to set a flag in memory somewhere that each IRET has to check for. So each IRET checks this flag and checks to see if it is the 'last' IRET. It is more efficient to let the LAPIC do this testing for you. So now we have to make this software LAPIC interrupt have a lower priority than IRQinterrupts. We do this by studying how the LAPIC assigns priority to interrupts. This is a bit lame but it works ok. The priority is based on the vector number we choose for the interrupt. Interrupt vectors are numbered 0x00 through 0xFF in Intel CPUs. The LAPIC assigns a priority based on the first of the two hex digits and ignores the second digit. Thus, any interrupts using vectors 0x50 through...
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