Relógio(simples) em vhdl

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.std_logic_arith.all; entity relogio is port( clk25: in bit; segm: out bit_vector(6 downto 0); disp: out bit_vector(3 downto 0); out_pin_led: out bit; b1: in bit; b2: in bit ); end relogio; architecture Behavioral of relogio is signal clk1, clk200: bit; signal segundos: integer range 0 to 59; signal unid, dez, cent, mil: integer range 0 to 9; function display(valor: integer range 0 to 9) return bit_vector is variable segmento: bit_vector(6 downto 0); begin case valor is when 0 => segmento := "0000001"; when 1 => segmento := "1001111"; when 2 => segmento := "0010010"; when 3 => segmento := "0000110"; when 4 => segmento := "1001100"; when 5 => segmento := "0100100"; when 6 => segmento := "1100000"; when 7 => segmento := "0001111"; when 8 => segmento := "0000000"; when 9 => segmento := "0001100"; when others => null; end case; return segmento; end function display; begin divisor1: process(clk25) variable conta: integer range 0 to 12500000; begin if(clk25'event and clk25='1')then if(conta < 12500000)then conta := conta+1; else conta := 0; clk1 <=not (clk1); end if; end if; end process divisor1; divisor2: process(clk25) variable conta: integer range 0 to 62500; begin if(clk25'event and clk25='1')then if(conta <62500)then conta := conta+1; else conta := 0; clk200 <= not(clk200); end if; end if; end process divisor2; principal: process(clk1) begin if(clk1'event and clk1 ='1')then