Analise de sistemas

ENEE 446: Digital Computer Design — The RiSC-16 Instruction-Set Architecture

The RiSC-16 Instruction-Set Architecture
ENEE 446: Digital Computer Design, Fall 2000 Prof. Bruce Jacob

1.

RiSC-16 Instruction Set

This paper describes the instruction set of the 16-bit Ridiculously Simple Computer (RiSC-16), a teaching ISA that is based on the Little Computer (LC-896) developed by Peter Chen at the University of Michigan. The RiSC-16 is an 8-register, 16-bit computer. All addresses are shortwordaddresses (i.e. address 0 corresponds to the first two bytes of main memory, address 1 corresponds to the second two bytes of main memory, etc.). Like the MIPS instruction-set architecture, by hardware convention, register 0 will always contain the value 0. The machine enforces this: reads to register 0 always return 0, irrespective of what has been written there. The RiSC-16 is very simple, but it is general enough to solve complex problems. There are three machine-code instruction formats and a total of 8 instructions. They are illustrated in the figure below.
Bit: 15 14 3 bits RRR-type: opcode 3 bits RRI-type: opcode 3 bits RI-type: Bit: 15 opcode 14 3 bits ADD: 000 3 bits ADDI: 001 3 bits NAND: 010 3 bits LUI: 011 3 bits SW: 100 3 bits LW: 101 3 bits BEQ: 110 3 bits JALR: Bit: 15 111 14 13 12 13 12 13 12 11 3 bits reg A 3 bits reg A 3 bits reg A 11 3 bits reg A 3 bits reg A 3 bits reg A 3 bits reg A 3 bits reg A 3 bits reg A 3 bits reg A 3 bits reg A 11 10 9 3 bits reg B 3 bits reg B 3 bits reg B 3 bits reg B 8 7 6 5 4 10 9 8 3 bits reg B 3 bits reg B 3 bits reg B 7 10 9 8 3 bits reg B 3 bits reg B 7 6 5 4 3 2 1 3 bits reg C 7 bits signed immediate (-64 to 63) 10 bits immediate (0 to 0x3FF) 6 5 4 3 2 1 3 bits reg C 7 bits signed immediate (-64 to 63) 4 bits 0 10 bits immediate (0 to 0x3FF) 7 bits signed immediate (-64 to 63) 7 bits signed immediate (-64 to 63) 7 bits signed immediate (-64 to 63) 7 bits 0 3 2 1 0 3 bits reg C 0 0

4 bits 0

FORMATS:

4 bits 0