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XXII Conference on Design of Circuits and Integrated Systems

ISBN-13 978-84690-8629-2

Dennis Andrade, Ferran Martorell, Francesc Moll, Antonio Rubio Technical University of Catalonia (UPC) Barcelona, Spain dam1029@eel.upc.edu
Abstract— The supply voltage decrease and power consumptionincrease of modern ICs made the requirements for low voltage fluctuation caused by packaging and on-chip parasitic impedances more difficult to achieve. Most of the research works on the area assume that all the nodes of the chip are fed at the same voltage, in such a way that the main cause of disturbance or fluctuation is the parasitic impedance of packaging. In the paper an approach to analyze theeffect of high and fast current demands on the on-chip power supply network. First an approach to model the entire network by considering a homogeneous conductive foil is presented. The modification of the timing parameters of flipflops caused by spatial voltage drops through the IC surface are also investigated. Index Terms— CMOS, integrated circuits ground bounce, power supply voltagefluctuations, noise, digital circuit performances.

the impact and cost of ground bounce and power supply fluctuations is one of the most active topics currently addressed by researchers [1, 2]. Typically, in many of these research works the mechanism of the voltage fluctuations is modeled by the use of a lumped and uni-dimensional serial electric circuit as shown in Fig. 1, taken from [3]. The VDD powersupply package pins are modeled by an inductance and a serial resistance together with a parasitic capacitance, all lumped components. Later, the power lines are applied to the digital cells with the consideration of a parasitic resistance for the distribution network and a capacitor resulting from the parasitic and on-chip decoupling capacitances. This model explains in a first approach the twocomponents of the voltage fluctuations: the IR drop caused by the current flow through the parasitic resistance of both package and power supply network and the LdI/dt component caused by the voltage drops in the package inductance due to the sharp and abrupt shape of the CMOS digital circuit current. From the lumped model it could be derived that the VDD and GND rails are equipotential for all thecells of the circuit. However, the real picture of the power structure clearly gives a different result. The distribution network is composed by a given number of crossed bars in one or two levels of metal, usually the upper levels, with delivering points of power supply at the crosses. The VDD (and GND) level is applied to the network from a large amount of VDD and GND pins located all around thepackage. For fast and non-homogeneous current demands both resistive and inductive drops inside the chip distribution network could appear caused by the distributed resistance and inductance of the network, causing the appearance of voltage drops through it (∆V(x,y,t)) and consequently through the logic system. The analysis of the voltage drop due to the distributed elements and its effects ondata transmission and storing in memory elements is the objective of this work. In this work we face the problem in two steps. First we model the RI and LdI/dt voltage drops in the internal power supply distribution network. In order to consider a general result, far from the casuistic details of real power distribution networks, we consider the network composed by two (VDD and GND) foils with thearea of the entire chip. In the second part of the work we present simulation results for the observation of the effect of internal voltage drops in the bus structure connecting two separated cores or functional units. The paper is organized as follows. Section II addresses the modeling of the power supply network as a conductive



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