Lpc2103 user manual

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UM10161
LPC2101/02/03 User manual
Rev. 4 — 13 May 2009 User manual

Document information Info Keywords Abstract Content LPC2101, LPC2102, LPC2103, ARM, ARM7, embedded, 32-bit, microcontroller LPC2101/02/03 User manual revision

NXP Semiconductors

UM10161
LPC2101/02/03 User manual

Revision history Rev 04 Date 20090513 Description LPC2101/02/03 User manual

Modifications:

• •
03Description of Deep power-down mode and power selector module added (LPC2101/02/03 revisions A and higher only). See Section 5–10, Section 18–6.14, and Section 18–7. Description of three CRP levels added (LPC2101/02/03 revisions A and higher only). See Section 19–8. 20081002 LPC2101/02/03 User manual

Modifications:

• • • • • • • • • • • •
02

Description of pins VBAT, RTCX1, RTCX2,VDDA, and VDD(1V8) updated. Bit description for bits CPOL and CPHA in SSPCR0 register updated. Pin description for ADC pins updated. PLCC44 pin configuration removed. HVQFN48 pin configuration added. I2C pin description in pin configuration updated. Timer2/3 register names PWM2/3CON updated. Description of JTAG pin TCK updated. Bit description in CTC register updated. Various editorial updates.Description of fractional baudrate generator updated for UART0 and UART1. Bit description of the PCONP register updated. 20070801 LPC2101/02/03 User manual

Modifications:


01

SCL1 and SDA1 pins described as not open-drain. 20060112 Initial version

Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to:salesaddresses@nxp.com
UM10161_4 © NXP B.V. 2009. All rights reserved.

User manual

Rev. 4 — 13 May 2009

2 of 292

UM10161
Chapter 1: LPC2101/02/03 Introductory information
Rev. 4 — 13 May 2009 User manual

1. Introduction
The LPC2101/02/03 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 8 kB, 16 kB, or 32 kB ofembedded high speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service routines and DSP algorithms, this increases performance up to 30 % over the Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % withminimal performance penalty. Due to their tiny size and low power consumption, LPC2101/02/03 are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. A blend of serial communications interfaces, ranging from multiple UARTS, SPI, and SSP to two I2Cs, and on-chip SRAM of 2/4/8 kB make these devices very well suited for communication gateways andprotocol converters. The superior performance also makes these devices suitable as math coprocessors. Various 32-bit and 16-bit timers, an improved 10-bit ADC, PWM features through output match on all timers, and 32 fast GPIO lines with up to 13 edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems.

2. How toread this manual
This user manual describes parts LPC2101/02/03 Revision ‘-’ and parts LPC2101/02/03 Revision A and higher. Differences between Revision ‘-’ and others are described at the beginning of each chapter if applicable and are summarized as follows: Revision ‘-’: One CRP level; Power-down modes: idle and power-down. Revision A and higher: Three CRP levels; Power-down modes: idle,power-down, and deep power-down.

3. Enhanced features
Starting with Revision A, the LPC2101/02/03 have the following enhanced features implemented:

• Deep power-down mode controlled by the RTC block. • Three levels of Code Read Protection (CRP).

4. Features
• 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP48 package. • 2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of...
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