Header file

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msp430g2553 /******************************************************** ************ * * Standard register and bit definitions for the Texas Instruments * MSP430 microcontroller. * * This file supports assembler and C development for * MSP430G2553 devices. * * Texas Instruments, Version 1.0 * * Rev. 1.0, Setup * ********************************************************* ***********/ #ifndef__MSP430G2553 #define __MSP430G2553 #ifdef __cplusplus extern "C" { #endif /*---------------------------------------------------------------------------*/ /* PERIPHERAL FILE MAP */ /*---------------------------------------------------------------------------*/ /* External references resolved by a device-specific linker command file */ #define SFR_8BIT(address) extern volatile unsigned char address #defineSFR_16BIT(address) extern volatile unsigned int address /******************************************************** **** * STANDARD BITS ********************************************************* ***/ #define BIT0 #define BIT1 (0x0001) (0x0002) Página 1

#define #define #define #define #define #define #define #define #define #define #define #define #define #define

BIT2 BIT3 BIT4 BIT5 BIT6 BIT7BIT8 BIT9 BITA BITB BITC BITD BITE BITF

msp430g2553 (0x0004) (0x0008) (0x0010) (0x0020) (0x0040) (0x0080) (0x0100) (0x0200) (0x0400) (0x0800) (0x1000) (0x2000) (0x4000) (0x8000)

/******************************************************** **** * STATUS REGISTER BITS ********************************************************* ***/ #define #define #define #define #define #define #define #define#define C Z N V GIE CPUOFF OSCOFF SCG0 SCG1 (0x0001) (0x0002) (0x0004) (0x0100) (0x0008) (0x0010) (0x0020) (0x0040) (0x0080)

/* Low Power Modes coded with Bits 4-7 in SR */ #ifdef __ASM_HEADER__ /* Begin #defines for assembler */ #define LPM0 (CPUOFF) #define LPM1 (SCG0+CPUOFF) #define LPM2 (SCG1+CPUOFF) #define LPM3 (SCG1+SCG0+CPUOFF) #define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) /* End #defines forassembler */ #else /* Begin #defines for C */ #define LPM0_bits (CPUOFF) #define LPM1_bits (SCG0+CPUOFF) #define LPM2_bits (SCG1+CPUOFF) #define LPM3_bits (SCG1+SCG0+CPUOFF) #define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) Página 2

msp430g2553 #include "in430.h" #define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ #define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit LowPower Mode 0 */ #define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ #define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ #define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ #define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ #define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ #defineLPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ #define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ #define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ #endif /* End #defines for C */ /******************************************************** **** * PERIPHERAL FILE MAP ********************************************************* ***//******************************************************** **** * SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS ********************************************************* ***/ SFR_8BIT(IE1); Interrupt Enable #define WDTIE Interrupt Enable #define OFIE Fault Interrupt #define NMIIE Interrupt Enable #define ACCVIE Access Violation SFR_8BIT(IFG1); Página 3 /* 1 */ (0x01) */ (0x02) Enable */ (0x10)*/ (0x20) Interrupt Enable */ /* Flash /* /* NMI /* Osc. /* Watchdog

msp430g2553 Interrupt Flag 1 */ #define WDTIFG Interrupt Flag */ #define OFIFG Fault Interrupt Flag */ #define PORIFG Interrupt Flag */ #define RSTIFG Interrupt Flag */ #define NMIIFG Interrupt Flag */ SFR_8BIT(IE2); Interrupt Enable 2 */ #define UC0IE #define UCA0RXIE #define UCA0TXIE #define UCB0RXIE #define UCB0TXIE...
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